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| 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs October 1998 Revised November 2000 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs General Description The LVTH125 contains four independent non-inverting buffers with 3-STATE outputs. These buffers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH125 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. Features s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 125 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number 74LVTH125M 74LVTH125SJ 74LVTH125MTC Package Number M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 114-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol IEEE/IEC Connection Diagram Truth Table Pin Descriptions Pin Names An, Bn On Description Inputs 3-STATE Outputs An L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance Inputs Bn L H X Output On L H Z (c) 2000 Fairchild Semiconductor Corporation DS012011 www.fairchildsemi.com 74LVTH125 Absolute Maximum Ratings(Note 1) Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 2) VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State mA mA mA mA mA V -0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50 64 128 64 128 -65 to +150 C Recommended Operating Conditions Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V - 2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA -32 64 -40 0 85 10 C ns/V t/V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. www.fairchildsemi.com 2 74LVTH125 DC Electrical Characteristics Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) II(OD) II Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ICC Power Off Leakage Current Power up/down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 6) Note 3: All typical values are at VCC = 3.3V, TA = 25C. Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. TA =-40C to +85C Min Typ (Note 3) -1.2 2.0 0.8 VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 0.19 5 0.19 0.19 0.2 A A A A A mA mA mA mA mA A A A V V V V V II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 4) (Note 5) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND Max Units Conditions 3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 (Note 7) TA = 25C Min Typ 0.8 -0.8 Max V V Units Conditions CL = 50 pF, RL = 500 (Note 8) (Note 8) Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW. 3 www.fairchildsemi.com 74LVTH125 AC Electrical Characteristics TA = -40C to +85C CL = 50 pF, RL = 500 Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 10) Output Disable Time Output Enable Time Propagation Delay Data to Output 1.0 1.0 1.0 1.1 1.5 1.3 VCC = 3.3V 0.3V Typ (Note 9) 3.5 3.9 4.0 4.0 4.5 4.5 1.0 1.0 1.0 1.0 1.1 1.5 1.3 4.5 4.9 5.5 5.4 5.7 4.0 1.0 ns ns ns ns Max VCC = 2.7V Min Max Units Note 9: All typical values are at VCC = 3.3V, TA = 25C. Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance Symbol CIN COUT (Note 11) Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF Input Capacitance Output Capacitance Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 4 74LVTH125 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com 74LVTH125 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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